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| Virtex-4 User Guide 0 R Virtex-4 Family Overview 0 0 DS112 (v1.1) September 10, 2004 Advance Product Specification General Description The Virtex-4TM Family is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or ASMBLTM column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families (platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of hard-IP core blocks complete the system solution. These cores include the PowerPCTM processors (with a new APU interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. Virtex-4 devices are produced on a state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC technology. Summary of Virtex-4 Features * Three families LX/SX/FX Virtex-4 LX: High-performance logic applications solution Virtex-4 FX: High-performance, full-featured solution for embedded platform applications Virtex-4 SX: High-performance solution for Digital Signal Processing (DSP) applications Digital Clock Manager (DCM) blocks Additional Phase-Matched Clock Dividers (PMCD) Differential Global Clocks 18x18, two's complement, signed Multiplier Optional pipeline stages Built-In Accumulator (48-bits) & Adder/Subtracter Distributed RAM Dual-Port 18-Kbit RAM blocks * Optional pipeline stages * Optional programmable FIFO logic - Automatically remaps RAM signals as FIFO signals High-speed memory interface support: DDR and DDR-2 SDRAM, QDR-II, RLDRAM-II, and FCRAM-II * SelectIO Technology 1.5 to 3.3 V I/O Operation Built-In ChipSyncTM Source-Synchronous Technology Digitally-controlled impedance (DCI) active termination Fine grained I/O banking (Configuration in one bank) * XesiumTM Clock Technology - * XtremeDSPTM Slice - * Smart RAM Memory Hierarchy - * * * * * * * * * Flexible Logic Resources Built-in System Monitor (voltage/temp. measurement) 10-bit, 200kSPS A/D Converter (ADC) Secure Chip AES Bitstream Encryption 90-nm copper CMOS process 1.2V core voltage Flip-Chip Packaging RocketIOTM 622 Mb/s to 11.1 Gb/s Multi-Gigabit Transceivers (MGT) (FX only) IBM PowerPC RISC Processor Core (FX only) PowerPC 405 (PPC405) Core Auxiliary Processor Unit Interface (User Coprocessor) - * Multiple Tri-Mode Ethernet MACs (FX only) Table 1: Virtex-4 FPGA Family Members Configurable Logic Blocks (CLBs)(1) Device Array Row x Col 64 x 24 96 x 28 128 x 36 128 x 52 160 x 56 192 x 64 192 x 88 192 x 116 Logic Cells 13,824 24,192 41,472 59,904 80,640 110,592 152,064 200,448 Block RAM Xtreme PowerPC RocketIO Total Max System ADC Ethernet Slices Max 18 Kb Max DCMs PMCDs DSP Processor Transciever I/O User Monitors Blocks MACs (2) Blocks Distributed Slices Block Blocks Blocks Banks I/O RAM (Kb) RAM (Kb) 6,144 10,752 18,432 26,624 35,840 49,152 67,584 89,088 96 168 288 416 560 768 1056 1392 32 48 64 64 80 96 96 96 48 72 96 160 200 240 288 336 864 1,296 1,728 2,880 3,600 4,320 5,184 6,048 4 8 8 8 12 12 12 12 0 4 4 4 8 8 8 8 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 9 11 13 13 15 17 17 17 320 448 640 640 768 960 960 960 XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 (c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS112 (v1.1) September 10, 2004 Advance Product Specification www.xilinx.com 21 Virtex-4 Family Overview Table 1: Virtex-4 FPGA Family Members (Continued) Configurable Logic Blocks (CLBs)(1) Device Array Row x Col 64 x 40 96 x 40 128 x 48 64 x 24 64 x 36 96 x 44 128 x 52 160 x 68 192 x 84 Logic Cells 23,040 34,560 55,296 12,312 19,224 41,904 56,880 94,896 142,128 R Block RAM Xtreme PowerPC RocketIO Total Max System ADC Ethernet Slices Max 18 Kb Max DSP DCMs PMCDs Processor Transciever I/O User Monitors Blocks MACs (2) Blocks Distributed Slices Block Blocks Blocks Banks I/O RAM (Kb) RAM (Kb) 160 240 384 86 134 243 395 659 987 128 192 512 32 32 48 128 160 192 128 192 320 36 68 144 232 376 552 2,304 3,456 5,760 648 1,224 2,592 4,176 6,768 9,936 4 8 8 4 4 8 12 12 20 0 4 4 0 0 4 8 8 8 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 N/A N/A N/A 1 1 2 2 2 2 N/A N/A N/A 2 2 4 4 4 4 N/A N/A N/A N/A 8 12 16 20 24 9 11 13 9 9 11 13 15 17 320 448 640 320 320 448 576 768 896 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 10,240 15,360 24,576 5,472 8,544 15,552 25,280 42,176 63,168 Notes: 1. One CLB = Four Slices = Maximum of 64 bits. 2. Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator 500 MHz Xesium Clock Technology * Up to twenty Digital Clock Manager (DCM) modules - Precision clock deskew and phase shift - Flexible frequency synthesis - Dual operating modes to ease performance trade-off decisions - Improved maximum input/output frequency - Improved phase shifting resolution - Reduced output jitter - Low-power operation - Enhanced phase detectors - Wide phase shift range Companion Phase-Matched Clock Divider (PMCD) blocks Differential clocking structure for optimized low-jitter clocking and precise duty cycle 32 Global Clock networks Regional I/O and Local clocks Up to 40% speed improvement over previous generation devices Up to 200,000 logic cells including: - Up to 178,176 internal registers with clock enable (XC4VLX200) - Up to 178,176 look-up tables (LUTs) - Logic expanding multiplexers and I/O registers Cascadable variable shift registers or distributed memory capability 500 MHz XtremeDSP Slices * * * * * * Dedicated 18-bit x 18-bit multiplier, multiply-accumulator, or multiply-adder blocks Optional pipeline stages for enhanced performance Optional 48-bit accumulator for multiply accumulate (MACC) operation Integrated adder for complex-multiply or multiply-add operation Cascadeable Multiply or MACC Up to 100% speed improvement over previous generation devices. Up to 10Mb of integrated block memory Optional pipeline stages for higher performance Multi-rate FIFO support logic - Full and Empty Flag support - Fully programmable AF and AE Flags - Synchronous/ Asynchronous Operation Dual-port architecture Independent read and write port width selection (RAM only) 18 Kbit blocks (memory and parity/sideband memory support) Configurations from 16K x 1 to 512 x 36 (4K x 4 to 512 x 36 for FIFO operation) Byte-write capability (connection to PPC405, etc.) Dedicated cascade routing to form 32K x 1 memory without using FPGA routing Up to 100% speed improvement over previous generation devices. 500 MHz Integrated Block Memory * * * * * * * * * Flexible Logic Resources * * * * * * * * 22 www.xilinx.com DS112 (v1.1) September 10, 2004 Advance Product Specification R Virtex-4 Family Overview SelectIO Technology * * * Up to 960 user I/Os Wide selections of I/O standards from 1.5V to 3.3V Extremely high-performance - 600 Mb/s HSTL & SSTL (on all single-ended I/O) - 1 Gb/s LVDS (on all differential I/O pairs) True differential termination Selected low-capacitance I/Os for improved signal integrity Same edge capture at input and output I/Os Memory interface support for DDR and DDR-2 SDRAM, QDR-II, RLDRAM-II, and FCRAM-II Integrated with SelectIO technology to simplify source-synchronous interfaces Per-bit deskew capability built in all I/O blocks (variable input delay line) Dedicated I/O and regional clocking resources (pin and trees) Built in data serializer/deserializer logic in all I/O and clock dividers Memory/Networking/Telecommunication interfaces up to 1 Gb/s+ Digitally Controlled Impedance (DCI) Active I/O Termination * * * * * * * * * * * * * Optional series or parallel termination Temperature compensation On-chip or off-chip temperature sensing capability On-chip or off-chip voltage monitoring capability Peak detect and alarm features Supplemental A/D converter block in selected devices 10-bit / 200 kilo samples per second (kSPS or KHz) Dedicated analog I/O pins 256-bit AES bitstream decryption provides intellectual property (IP) security Improved bitstream error detection/correction capability Fast SelectMAP configuration JTAG support Readback capability System Monitor * * * * A/D Converter Blocks ChipSync Technology * * * * * Configuration 90 nm Copper CMOS Process 1.2V Core Voltage System Blocks Specific to the FX Family RocketIO Multi-Gigabit Transceiver (MGT) * * * * * * * * * * * Full-duplex serial transceiver (MGT) capable of 622 Mb/s to 11.1 Gb/s baud rates 8b/10b, 64b/66b, user-defined FPGA logic, or no data encoding Channel bonding support CRC generation and checking Programmable pre-emphasis or pre-equalization for the transmitter Programmable continuous time equalization for the receiver Programmable discrete feedback equalization for the receiver On-chip AC coupled receiver Receiver signal detect and loss of signal indicator Transmit driver sleep mode User dynamic reconfiguration using secondary configuration bus PowerPC 405 RISC Core * Embedded PowerPC 405 (PPC405) core - Up to 450 MHz operation - Five-stage data path pipeline - 16 KB instruction cache - 16 KB data cache - Enhanced instruction and data on-chip memory (OCM) controllers - Additional frequency ratio options between PPC405 and Processor Local Bus Auxiliary Processor Unit (APU) Interface for direct connection from PPC405 to coprocessors in fabric - APU can run at different clock rates - Supports autonomous instructions: no pipeline stalls - 32-bit instruction and 64-bit data - 4-cycle cache line transfer * DS112 (v1.1) September 10, 2004 Advance Product Specification www.xilinx.com 23 Virtex-4 Family Overview R Tri-mode Ethernet Media Access Controller * * * * * * IEEE 802.3 compliant Operates at 10, 100, and 1,000 Mb/s Supports tri-mode auto-detect Receive address filter (16 address entries) Fully monolithic 1000Base-X solution with RocketIO MGT Implements SGMII through RocketIO MGT to external PHY device * * * * * Supports multiple PHY (MII, GMII, etc.) interfaces through an I/O resource Receive and transmit statistics available through separate interfaces Separate host and client interfaces Support for jumbo frames Flexible, user-configurable host interface Architectural Description Virtex-4 Array Overview Virtex-4 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-4 devices implement the following functionality: * I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by programmable I/O blocks (IOBs). The IOBs are enhanced for source-synchronous applications. Source-synchronous optimizations include per-bit deskew, data serializer/deserializer, clock dividers, and dedicated local clocking resources. Configurable Logic Blocks (CLBs), the basic logic elements for Xilinx FPGAs, provide combinatorial and synchronous logic as well as distributed memory and SRL16 shift register capability. Block RAM modules provide flexible 18Kbit true dual-port RAM, that are cascadable to form larger memory blocks. In addition, Virtex-4 block RAMs contain optional programmable FIFO logic for increased device utilization. Cascadable embedded XtremeDSP slices with 18-bit x 18-bit dedicated multipliers, integrated Adder, and 48-bit accumulator. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication/division, and coarse-/fine-grained clock phase shifting. * System Monitor - Differential analog channels plus on-chip temperature and supply voltage monitors - Dedicated analog-only chip input channel is provided for precision off-chip monitoring - Allows monitoring of on-chip or off-chip voltages and temperatures - Alarm and peak detect functionality 10-bit, 200 kSPS analog-to-digital converter in larger devices. * Additionally, FX devices support the following embedded system functionality: * * * Integrated high-speed serial transceivers enable data rates up to 11.1 Gb/s per channel. Embedded IBM PowerPC 405 RISC CPU (up to 450 MHz) with the auxiliary processor unit interface 10/100/1000 Ethernet media-access control (EMAC) cores. * * * The general routing matrix (GRM) provides an array of routing switches between each component. Each programmable element is tied to a switch matrix, allowing multiple connections to the general routing matrix. The overall programmable interconnection is hierarchical and designed to support high-speed designs. All programmable elements, including the routing resources, are controlled by values stored in static memory cells. These values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements. * 24 www.xilinx.com DS112 (v1.1) September 10, 2004 Advance Product Specification R Virtex-4 Family Overview Virtex-4 Features This section briefly describes the features of the Virtex-4 family of FPGAs. Input/Output Blocks (SelectIO) IOBs are programmable and can be categorized as follows: * * * * * * * Programmable single-ended or differential (LVDS) operation Input block with an optional single data rate (SDR) or double data rate (DDR) register Output block with an optional SDR or DDR register Bidirectional block Per-bit deskew circuitry Dedicated I/O and regional clocking resources Built in data serializer/deserializer General purpose I/O in select locations (four per bank) are designed to be "regional clock capable" I/O by adding special hardware connections for I/O in the same locality. These regional clock inputs are distributed within a limited region to minimize clock skew between IOBs. Regional I/O clocking supplements the global clocking resources. Data serializer/deserializer capability is added to every I/O to support source synchronous interfaces. A serial-to-parallel converter with associated clock divider is included in the input path, and a parallel-to-serial converter in the output path. An in-depth guide to the Virtex-4 IOB is discussed in the Virtex-4 User Guide. The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches. IOBs support the following single-ended standards: * * * * * * * LVTTL LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) PCI (33 and 66 MHz) PCI-X GTL and GTLP HSTL 1.5V and 1.8V (Class I, II, III, and IV) SSTL 1.8V and 2.5V (Class I and II) Configurable Logic Blocks (CLBs) A CLB resource is made up of four slices. Each slice is equivalent and contains: * * * * * * Two function generators (F & G) Two storage elements Arithmetic logic gates Large multiplexers Fast carry look-ahead chain Horizontal cascade chain The DCI I/O feature can be configured to provide on-chip termination for each single-ended I/O standard and some differential I/O standards. The IOB elements also support the following differential signaling I/O standards: * * * * * * LVDS and Extended LVDS (2.5V only) BLVDS (Bus LVDS) ULVDS HypertransportTM Differential HSTL 1.5V and 1.8V (Class II) Differential SSTL 1.8V and 2.5V (Class II) The function generators F & G are configurable as 4-input look-up tables (LUTs). Two slices in a CLB can have their LUTs configured as 16-bit shift registers, or as 16-bit distributed RAM. In addition, the two storage elements are either edge-triggered D-type flip-flops or level sensitive latches. Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources. The Virtex-4 CLBs are further discussed in the Virtex-4 User Guide. Block RAM The block RAM resources are 18 Kb true dual-port RAM blocks, programmable from 16K x 1 to 512 x 36, in various depth and width configurations. Each port is totally synchronous and independent, offering three "read-during-write" modes. Block RAM is cascadable to implement large embedded storage blocks. Additionally, back-end pipeline registers, clock control circuitry, built-in FIFO support, and byte write enable are new features supported in the Virtex-4 FPGA. The block RAM feature in Virtex-4 devices is further discussed in the Virtex-4 User Guide. Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the routing resources. Per-bit deskew circuitry allows for programmable signal delay internal to the FPGA. Per-bit deskew flexibly provides fine-grained increments of delay to carefully produce a range of signal delays. This is especially useful for synchronizing signal edges in source synchronous interfaces. DS112 (v1.1) September 10, 2004 Advance Product Specification www.xilinx.com 25 Virtex-4 Family Overview R XtremeDSP Slices The XtremeDSP slices contain a dedicated 18 x 18-bit 2's complement signed multiplier, adder logic, and a 48-bit accumulator. Each multiplier or accumulator can be used independently. These blocks are designed to implement extremely efficient and high-speed DSP applications. The block DSP feature in Virtex-4 devices are further discussed in XtremeDSP Design Considerations. System Monitor The basic building block of any digital system monitoring function is an Analog-to-Digital Converter (ADC). The ADC is capable of capturing 10-bits of information at 200 Ksps. Additional circuitry is used to monitor various parameters. System Monitor features include on-chip/off-chip supply voltage and temperature monitoring, and supply voltage peak / sag capture. A stand-alone ADC is available in the larger devices. The Virtex-4 System Monitor is covered in depth in the Virtex-4 User Guide. Global Clocking The DCM and global-clock multiplexer buffers provide a complete solution for designing high-speed clock networks. Up to twenty DCM blocks are available. To generate deskewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also provides 90, 180, and 270 phase-shifted versions of the output clocks. Fine-grained phase shifting offers higher resolution phase adjustment with fraction of the clock period increments. Flexible frequency synthesis provides a clock output frequency equal to a fractional or integer multiple of the input clock frequency. Virtex-4 devices have 32 global-clock MUX buffers. The clock tree is designed to be differential. Differential clocking helps reduce jitter and duty cycle distortion. Boundary Scan Boundary-scan instructions and associated data registers support a standard methodology for accessing and configuring Virtex-4 devices, complying with IEEE standards 1149.1 and 1532. Configuration Virtex-4 devices are configured by loading the bitstream into internal configuration memory using one of the following modes: * * * * * Slave-serial mode Master-serial mode Slave SelectMAP mode Master SelectMAP mode Boundary-scan mode (IEEE-1532) Routing Resources All components in Virtex-4 devices use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the performance for high-speed designs. Optional 256-bit AES decryption is supported on-chip (with software bitstream encryption) providing Intellectual Property security. Virtex-4 FX Family This section briefly describes blocks available only in FX devices. RocketIO Multi-Gigabit Transceiver 8 - 24 Channels RocketIO Multi-Gigabit Serial Transceivers (MGTs) capable of running 622 Mb/s - 11.1 Gb/s * * * * * * Full Clock and Data Recovery 32-bit or 40-bit datapath support Optional 8b/10b, 64b/66b, or FPGA-based encode/decode Integrated FIFO/Elastic Buffer Support for Channel Bonding Embedded 32-bit CRC generation/checking * * * * Integrated Comma-detect or programmable A1/A2, A1A1/A2A2 detection Programmable pre-emphasis (AKA transmitter equalization) Programmable receiver equalization Embedded support for: - Out of Band (OOB) Signalling: Serial ATA - Beaconing and Electrical Idle: PCI-ExpressTM On-chip bypassable AC coupling for receiver * 26 www.xilinx.com DS112 (v1.1) September 10, 2004 Advance Product Specification R Virtex-4 Family Overview One or Two PowerPC 405 Processor Cores * * * 32-bit Harvard Architecture 5-Stage Execution Pipeline Integrated 16KB Level 1 Instruction Cache and 16KB Level 1 Data Cache - Integrated Level 1 Cache Parity Generation and Checking CoreConnectTM Bus Architecture Efficient, high-performance on-chip memory (OCM) interface to block RAM PLB Synchronization Logic (Enables Non-Integer CPU-to-PLB Clock Ratios) Auxiliary Processor Unit (APU) Interface and Integrated APU Controller - Optimized FPGA-based Coprocessor connection * Automatic decode of PowerPC floating-point instructions - Allows custom instructions (Decode for up to eight instructions) - Extremely efficient microcontroller-style interfacing Two or Four Tri-Mode (10/100/1000 Mb/s) Ethernet Media Access Control (MAC) Cores * * * * * * IEEE 802.3-2000 Compliant MII/GMII Interface or SGMII (when used with RocketIO Transceivers) Can Operate Independent of PowerPC processor Half or Full Duplex Supports Jumbo Frames 1000 Base-X PCS/PMA: When used with RocketIO MGT can provide complete 1000 Base-X implementation on-chip * * * * Intellectual Property Cores Xilinx offers IP cores for commonly used complex functions including DSP, bus interfaces, processors, and processor peripherals. Using Xilinx LogiCORETM products and cores from third party AllianceCORE participants, customers can shorten development time, reduce design risk, and obtain superior performance for their designs. Additionally, our CORE GeneratorTM system allows customers to implement IP cores into Virtex-4 FPGAs with predictable and repeatable performance. It offers a simple user interface to generate parameter-based cores optimized for our FPGAs. The System Generator for DSP tool allows system architects to quickly model and implement DSP functions using handcrafted IP, and features an interface to third-party system level DSP design tools. System Generator for DSP implements many of the high-performance DSP cores supporting Virtex-4 FPGAs including the Xilinx Forward Error Correction Solution with Interleaver/De-interleaver, Reed-Solomon encoder/decoders, and Viterbi decoders. These are ideal for creating highly-flexible, concatenated codecs to support the communications market. Industry leading connectivity and networking IP cores include the electronics industry's first Advanced Switching product, leading-edge PCI Express, Serial RapidIO, Fibre Channel, and 10Gb Ethernet cores that include Virtex-4 RocketIO multi-gigabit serial interfaces. The Xilinx SPI-4.2 IP core utilizes the Virtex-4 embedded ChipSync technology to implement dynamic phase alignment for high-performance source-synchronous operation. MicroBlazeTM 32-bit core provides the industry's fastest soft processing solution for building complex systems for the networking, telecommunication, data communication, embedded and consumer markets. The MicroBlaze processor features a RISC architecture with Harvard-style separate 32-bit instruction and data busses running at full speed to execute programs and access data from both on-chip and external memory. A standard set of peripherals are also CoreConnectTM enabled to offer MicroBlaze designers compatibility and reuse. All IP cores for Virtex-4 FPGAs are found on the Xilinx IP Center Internet portal presenting the latest intellectual property cores and reference designs via Smart Search for faster access. Application Notes and Reference Designs Application notes and reference designs written specifically for the Virtex-4 family are available on the Xilinx web site at: http://www.xilinx.com/virtex4 DS112 (v1.1) September 10, 2004 Advance Product Specification www.xilinx.com 27 Virtex-4 Family Overview R Virtex-4 Device and Package Combinations and Maximum I/Os Table 2: Virtex-4 Device and Package Combinations and Maximum Available I/Os Package Size Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12(1) XC4VFX20(1) XC4VFX40(1) XC4VFX60(1) XC4VFX100(1) XC4VFX140(1) Notes: 1. These package/part combinations and the quantity of MGTs and I/Os are not final numbers. N/A 240 8 12 12 320 352 352 12 16 20 448 576 576 20 24 768 768 24 896 N/A 320 N/A N/A 320 448 N/A 640 SF363 17 x 17 MGTs N/A N/A I/O 240 240 FF672 27 x 27 MGTs I/O FF668 27 x 27 MGTs N/A N/A N/A N/A I/O 320 448 448 448 N/A N/A N/A N/A N/A 640 640 768 768 768 N/A N/A N/A 960 960 960 FF1148 35 x 35 MGTs I/O FF1152 35 x 35 MGTs I/O FF1513 40 x 40 MGTs I/O FF1517 40 x 40 MGTs I/O FF1760 42.5 x 42.5 MGTs I/O Virtex-4 Ordering Information Virtex-4 ordering information is shown in Figure 1. Example: XC4VLX25-10FF668C Device Type Speed Grade (-10, -11, -12*) Temperature Range: C = Commercial (TJ = 0C to +85C) I = Industrial* (TJ = -40C to +100C) Number of Pins *NOTE: -12 devices not available in Industrial grade. Package Type DS112_01_062604 Figure 1: Virtex-4 Ordering Information 28 www.xilinx.com DS112 (v1.1) September 10, 2004 Advance Product Specification R Virtex-4 Family Overview Revision History The following table shows the revision history for this document. Date 08/02/04 09/10/04 Version 1.0 1.1 Revision Initial Xilinx release. Printed Handbook version. Typographical edits. Virtex-4 Documentation Complete and up-to-date documentation of the Virtex-4 family of FPGAs is available on the Xilinx web site. In addition to the most recent Virtex-4 Family Overview, the following files are also available for download: Virtex-4 Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-4 family. Virtex-4 User Guide This guide includes chapters on: * * * * * * * * * Clocking Resources Digital Clock Manager (DCM) Phase-Matched Clock Dividers (PMCD) Block RAM and FIFO memory Configurable Logic Blocks (CLBs) SelectIO Resources SelectIO Logic Resources Advanced SelectIO Logic Resources System Monitor Virtex-4 Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques. Virtex-4 Packaging Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. Virtex-4 PCB Designer's Guide This guide describes PCB guidelines for the Virtex-4 family. It covers SelectIO signaling, RocketIO signaling, power distribution systems, PCB breakout, and parts placement. Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide This guide describes the RocketIO Multi-Gigabit Transceivers available in the Virtex-4 FX family. Virtex-4 Tri-mode Ethernet Media Access Controller This guide describes the Tri-mode Ethernet Media Access Controller available in the Virtex-4 FX family. PowerPC 405 Processor Block Reference Guide This guide is updated to include the PowerPC 405 processor block available in the Virtex-4 FX family. XtremeDSP Design Considerations This guide describes the DSP48 slice and includes reference designs for using DSP48 math functions and various FIR filters. DS112 (v1.1) September 10, 2004 Advance Product Specification www.xilinx.com 29 Virtex-4 Family Overview R 30 www.xilinx.com DS112 (v1.1) September 10, 2004 Advance Product Specification |
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